(1) Field of the Invention
The present invention relates to a field effect transistor and a method of manufacturing the field effect transistor, and particularly relates to a field effect transistor composed of a group III nitride semiconductor and a method of manufacturing the field effect transistor.
(2) Description of the Related Art
In recent years, field effect transistors (FET) as power switching devices using gallium nitride (GaN) based materials have been actively researched. Nitride semiconductor materials such as GaN can be combined with aluminum nitride (AlN) or indium nitride (InN) to form various mixed crystals, and thus can form a heterojunction similarly to the arsenic-based semiconductor material such as conventional gallium arsenide (GaAs). Especially, the heterojunction of a nitride semiconductor has such characteristics that high concentrations of carriers occur at the hetero-interface due to spontaneous polarization and piezoelectric polarization even in a state where the heterojunction is not doped. Consequently, in the case where an FET is made of nitride semiconductor material, the FET tends to be depletion type (normally-on), thus it is difficult to obtain an enhancement type (normally-off) characteristics. However, most devices currently used in the power electronics market are normally-off, which is highly demanded for an FET made of GaN-based nitride semiconductor materials.
Examples of methods for achieving a normally-off FET include a method of shifting a threshold voltage to a higher level by using recessed gate (for example, see T. Kawasaki et al, “Solid State Devices and Materials”, 2005, tech. digest, pp 206, hereinafter referred to as Non-Patent Reference 1), and another method of fabricating the FET on the (10-12) plane of a sapphire substrate so that no polarization electric field is generated in the crystal growth direction of a nitride semiconductor (for example, see M. Kuroda et al, “Solid State Devices and Materials”, 2005, tech. digest, pp 470, hereinafter referred to as Non-Patent Reference 2). As a promising structure for normally-off FET, Junction Field Effect Transistor (JFET) in which p-type GaN layer is formed in the gate has been proposed (for example, see Japanese Unexamined Patent Application Publication No. 2005-244072, hereinafter referred to as Patent Reference 1).
FIG. 7 shows a cross-sectional view of the JFET in Patent Reference 1.
In the JFET, an AlN buffer layer 602, an undoped GaN layer 603, an undoped AlGaN barrier layer 604, and a p-type GaN layer 605 are sequentially formed on a substrate 601 composed of sapphire. Furthermore, a gate electrode 608 is formed on the p-type GaN layer 605; and a source electrode 606 and a drain electrode 607 are formed on the undoped AlGaN barrier layer 604.
In the JFET, the piezoelectric polarization occurred in the heterojunction interface between the undoped GaN layer 603 and the undoped AlGaN barrier layer 604 is cancelled by the piezoelectric polarization occurred in the heterojunction interface between the undoped AlGaN barrier layer 604 and the p-type GaN layer 605. Thereby, two-dimensional electron gas density immediately below the gate electrode 608 can be reduced, and normally-off characteristics can be achieved. In addition, by using a p-n junction with a built-in potential greater than that of Schottky junction for the gate, the gate turn on voltage can be increased, which is advantageous in reducing the gate leakage current even with a positive gate voltage applied.